For system-on-chip (SOC) applications, it is desirable to integrate many functional blocks into a single integrated circuit. The most commonly used blocks include a microprocessor or micro-controller, static random access memory (SRAM) blocks, non-volatile memory blocks, and various special function logic blocks. However, traditional non-volatile memory processes, which typically use stacked gate or split-gate memory cells, are not compatible with a conventional logic process.
The combination of a non-volatile memory process and a conventional logic process results in a much more complicated and expensive “merged non-volatile memory and logic” process to implement system-on-chip integrated circuits. This is undesirable, because the typical usage of the non-volatile memory block in an SOC application is small in relation to the overall chip size.
Various proposals have been put forward in the past. FIG. 1 is a top view of a non-volatile cell V0 capable of being integrated into CMOS logic process, as proposed by Han et al. in U.S. Pat. No. 6,788,574. Non-volatile memory cell V0 includes a coupling capacitor, a read transistor and a tunneling capacitor. More specifically, non-volatile memory cell V0 includes N-well regions 11 and 12, N+ active regions 21-24, N+ contacts 31-34, P+ active regions 41-42, P+ contacts 51-52, and a polysilicon floating gate 60. Polysilicon floating gate 60 is substantially N+ polysilicon, with the exception of P+ polysilicon regions 65A and 65B and N+ polysilicon region 62. Polysilicon floating gate 60 forms a coupling capacitor gate 61, a read transistor gate 62 and a tunneling capacitor gate 63. A P-type channel region (not shown) exists between N+ active regions 23 and 24 of the read transistor.
Polysilicon floating gate 60 is deposited onto an insulating material (not shown) that separates the coupling capacitor gate 61, read transistor gate 62 and tunneling capacitor gate 63 from the underlying active regions. Coupling capacitor gate 61 acts as a first plate of the coupling capacitor and P+ active region 41 (which abuts N+ active region 21) acts as the second plate of the coupling capacitor. N+ contacts 31 and P+ contact 51 are electrically connected to form a common terminal. Tunneling capacitor gate 63 acts as a first plate of the tunneling capacitor and P+ active region 42 (which abuts N+ active region 22) acts as the second plate of the tunneling capacitor. N+ contact 32 and P+ contact 52 are electrically connected to form a common terminal. The operation of non-volatile memory cell V0 is described in detail in U.S. Pat. No. 6,788,574.
Non-volatile memory cell V0 has several limitations. First, the coupling capacitor is a large area MOS structure. Consequently, when the coupling capacitor operates in depletion mode, the capacitance of this structure is decreased, and the gate voltage control is degraded. Second, non-volatile memory cell V0 contains at least two independent N-Well regions 11 and 12, thereby increasing cell size. Finally, the usage of N+ polysilicon for a large area of capacitor control gate 61 increases the gate oxide leakage of memory cell V0, as it is well known that N+ polysilicon gates conduct significantly more current than P+ polysilicon gates, when biased in inversion mode. (See, e.g., Shi et al., “Polarity-Dependent Tunneling Current and Oxide Breakdown in Dual-Gate CMOSFET's”, IEEE Electron Device Letters, vol. 19, No. 10, October 1998, pp. 391-393.) This compromises data retention of non-volatile memory cell V0.
It would therefore be desirable to have a method and structure for implementing a non-volatile memory array on an integrated circuit that is fabricated using a conventional logic process and circumvents the limitations introduced by the prior art.